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? semiconductor components industries, llc, 2009 november, 2009 ? rev. 9 1 publication order number: ncp3063/d ncp3063, ncp3063b, ncv3063 1.5 a, step-up/down/ inverting switching regulators the ncp3063 series is a higher frequency upgrade to the popular mc34063a and mc33063a monolithic dc ? dc converters. these devices consist of an internal temperature compensated reference, comparator, a controlled duty cycle oscillator with an active current limit circuit, a driver and a high current output switch. this series was specifically designed to be incorporated in step ? down, step ? up and voltage ? inverting applications with a minimum number of external components. features ? operation to 40 v input ? low standby current ? output switch current to 1.5 a ? output voltage adjustable ? frequency operation of 150 khz ? precision 1.5% reference ? new features: internal thermal shutdown with hysteresis new features: cycle ? by ? cycle current limiting ? pb ? free packages are available applications ? step ? down, step ? up and inverting supply applications ? high power led lighting ? battery chargers figure 1. typical buck application circuit l reference d comparator 5 r2 r s q set dominant + ? 7 comparator ct 3 rs 1.25 v 8 ncp3063 regulator tsd 0.2 v + ? 2 6 r1 r s q 4 1 12 v ct 2.2 nf oscillator 47 h v out 3.3 v / 800 ma + 470 f c out v in + 220 f c in set dominant 0.15 3.9 k 2.4 k pdip ? 8 p, p1 suffix case 626 http://onsemi.com marking diagrams dfn ? 8 case 488af soic ? 8 d suffix case 751 1 8 ncp3063x awl yywwg ncp3063x = specific device code x = b a = assembly location l, wl = wafer lot y, yy = year w, ww = work week = pb ? free package (note: microdot may be in either location) see detailed ordering and shipping information in the package dimensions section on p age 16 of this data sheet. ordering information v3063 alyw 1 3063x alyw 1 ncv3063 awl yywwg 1 1 1 8 ncp 3063x alyw ncp 3063 alyw 1
ncp3063, ncp3063b, ncv3063 http://onsemi.com 2 figure 2. pin connections timing capacitor comparator inverting input v cc n.c. i pk sense gnd switch emitter switch collector (top view) 4 3 2 1 5 6 7 8 ? ? ? ? ?? ?? ?? ?? figure 3. pin connections note: ep flag must be tied to gnd pin 4 on pcb ep flag figure 4. block diagram reference comparator 5 r s q set dominant + ? 7 comparator ct 3 1.25 v 8 ncp3063 regulator tsd 0.2 v + ? 2 6 r s q 4 1 oscillator switch collector switch emitter timing capacitor gnd comparator inverting input +v cc i pk sense n.c. set dominant
ncp3063, ncp3063b, ncv3063 http://onsemi.com 3 pin description pin no. pin name description 1 switch collector internal darlington switch collector 2 switch emitter internal darlington switch emitter 3 timing capacitor oscillator input timing capacitor 4 gnd ground pin for all internal circuits 5 comparator inverting input inverting input pin of internal comparator 6 v cc voltage supply 7 i pk sense peak current sense input to monitor the voltage drop across an external resistor to limit the peak current through the circuit 8 n.c. pin not connected exposed pad exposed pad the exposed pad beneath the package must be connected to gnd (pin 4). additionally, using proper layout techniques, the exposed pad can greatly enhance the power dissipation capabilities of the ncp3063. maximum ratings (measured vs. pin 4, unless otherwise noted) rating symbol value unit v cc pin 6 v cc 0 to +40 v comparator inverting input pin 5 v cii ? 0.2 to + v cc v darlington switch collector pin 1 v swc 0 to +40 v darlington switch emitter pin 2 (transistor off) v swe ? 0.6 to + v cc v darlington switch collector to emitter pin 1 ? 2 v swce 0 to +40 v darlington switch current i sw 1.5 a i pk sense pin 7 v ipk ? 0.2 to v cc + 0.2 v timing capacitor pin 3 v tcap ? 0.2 to +1.4 v power dissipation and thermal characteristics rating symbol value unit pdip ? 8 thermal resistance, junction ? to ? air r ja 100 c/w soic ? 8 thermal resistance, junction ? to ? air thermal resistance, junction ? to ? case r ja r jc 180 45 c/w dfn ? 8 thermal resistance, junction ? to ? air r ja 80 c/w storage temperature range t stg ? 65 to +150 c maximum junction temperature t j max +150 c operating junction temperature range (note 3) ncp3063 ncp3063b, ncv3063 t j 0 to +70 ? 40 to +125 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. this device series contains esd protection and exceeds the following tests: pin 1 ? 8: human body model 2000 v per aec q100 ? 002; 003 or jesd22/a114; a115 machine model method 200 v 2. this device contains latch ? up protection and exceeds 100 ma per jedec standard jesd78. 3. the relation between junction temperature, ambient temperature and total power dissipated in ic is t j = t a + r ? p d 4. the pins which are not defined may not be loaded by external signals
ncp3063, ncp3063b, ncv3063 http://onsemi.com 4 electrical characteristics (v cc = 5.0 v, t j = t low to t high [note 5], unless otherwise specified) symbol characteristic conditions min typ max unit oscillator f osc frequency (v pin 5 = 0 v, ct = 2.2 nf, t j = 25 c) 110 150 190 khz i dischg / i chg discharge to charge current ratio (pin 7 to v cc , t j = 25 c) 5.5 6.0 6.5 ? i dischg capacitor discharging current (pin 7 to v cc , t j = 25 c) 1650 a i chg capacitor charging current (pin 7 to v cc , t j = 25 c) 275 a v ipk(sense) current limit sense voltage (t j = 25 c) (note 6) 165 200 235 mv output switch (note 7) v swce(drop) darlington switch collector to emitter voltage drop (i sw = 1.0 a, pin 2 to gnd, t j = 25 c) (note 7) 1.0 1.3 v i c(off) collector off ? state current (v ce = 40 v) 0.01 100 a comparator v th threshold voltage t j = 25 c 1.250 v ncp3063 ? 1.5 +1.5 % ncp3063b, ncv3063 ? 2 +2 % reg line threshold voltage line regulation (v cc = 5.0 v to 40 v) ? 6.0 2.0 6.0 mv i cii in input bias current (v in = v th ) ? 1000 ? 100 1000 na total device i cc supply current (v cc = 5.0 v to 40 v, ct = 2.2 nf, pin 7 = v cc , v pin 5 > v th , pin 2 = gnd, remaining pins open) 7.0 ma thermal shutdown threshold 160 c hysteresis 10 c 5. ncp3063: t low = 0 c, t high = +70 c; ncp3063b, ncv3063: t low = ? 40 c, t high = +125 c 6. the v ipk(sense) current limit sense v oltage is specified at static conditions. in dynamic operation the sensed current turn ? off value depends on comparator response time and di/dt current slope. see the operating description section for details. 7. low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient temperature as poss ible. 8. ncv prefix is for automotive and other applications requiring site and change control.
ncp3063, ncp3063b, ncv3063 http://onsemi.com 5 figure 5. oscillator frequency vs. oscillator timing capacitor figure 6. oscillator frequency vs. supply voltage ct, capacitance (nf) v cc , supply voltage (v) 40 29 25 16 12 7 3 110 120 130 150 160 170 180 190 figure 7. emitter follower configuration output darlington switch voltage drop vs. temperature figure 8. common emitter configuration output darlington switch voltage drop vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 150 100 50 0 ? 50 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 150 100 50 0 ? 50 1.0 1.05 1.10 1.15 1.20 1.25 figure 9. emitter follower configuration output darlington switch voltage drop vs. emitter current figure 10. common emitter configuration output darlington switch voltage drop vs. collector current i e , emitter current (a) i c , collector current (a) 1.5 1.0 0.5 0 1.0 1.1 1.2 1.3 1.5 1.7 1.8 2.0 1.5 1.0 0.5 0 0.5 0.6 0.7 0.8 0.9 1.1 1.4 1.5 frequency (khz) frequency (khz) 21 34 38 140 c t = 2.2 nf t j = 25 c voltage drop (v) v cc = 5.0 v i e = 1 a voltage drop (v) v cc = 5.0 v i c = 1 a voltage drop (v) voltage drop (v) 1.4 1.6 1.9 1.0 1.3 1.2 v cc = 5.0 v t j = 25 c v cc = 5.0 v t j = 25 c 0 50 100 150 200 250 300 350 400 450 0 1 2 3 4 5 6 7 8 9 10 11 12 1314 1516 1718 1920
ncp3063, ncp3063b, ncv3063 http://onsemi.com 6 figure 11. comparator threshold voltage vs. temperature figure 12. current limit sense voltage vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 95 35 20 5 ? 25 ? 40 1.20 1.22 1.24 1.26 1.28 1.30 125 50 35 5 ? 10 ? 25 ? 40 0.10 0.12 0.14 0.18 0.20 0.22 0.28 0.30 figure 13. standby supply current vs. supply voltage v cc , supply voltage (v) 38 33 28 8.0 3.0 2.0 2.5 3.0 3.5 4.5 5.0 5.5 6.0 v th , comparator threshold voltage (v) v ipk(sense) , current limit sense voltage (v) 20 95 110 0.16 i cc , supply current (ma) c t = 2.2 nf pin 5, 7 = v cc pin 2 = gnd ? 10 80 65 50 110 0.26 0.24 65 80 13 18 23 43 4.0
ncp3063, ncp3063b, ncv3063 http://onsemi.com 7 introduction the ncp3063 is a monolithic power switching regulator optimized for dc to dc converter applications. the combination of its features enables the system designer to directly implement step ? up, step ? down, and voltage ? inverting converters with a minimum number of external components. potential applications include cost sensitive consumer products as well as equipment for industrial markets. a representative block diagram is shown in figure 4. operating description the ncp3063 is a hysteretic, dc ? dc converter that uses a gated oscillator to regulate output voltage. in general, this mode of operation is somewhat analogous to a capacitor charge pump and does not require dominant pole loop compensation for converter stability. the t ypical operating waveforms are shown in figure 14. the output voltage waveform shown is for a step ? down converter with the ripple and phasing exaggerated for clarity. during initial converter startup, the feedback comparator senses that the output voltage level is below nominal. this causes the output switch to turn on and off at a frequency and duty cycle controlled by the oscillator, thus pumping up the output filter capacitor. when the output voltage level reaches nominal, the output switch next cycle turning on is inhibited. the feedback comparator will enable the sw itching immediately when the load current causes the output voltage to fall below nominal. under these conditions, output switch conduction can be enabled for a partial oscillator cycle, a partial cycle plus a complete cycle, multiple cycles, or a partial cycle plus multiple cycles. (see an920/d for more information). oscillator the oscillator frequency and off ? time of the output switch are programmed by the value selected for timing capacitor c t . capacitor c t is charged and dischar ged by a 1 to 6 ratio internal current source and sink, generating a positive going sawtooth waveform at pin 3. this ratio sets the maximum t on /(t on + t off ) of the switching converter as 6/(6 + 1) or 0.857 (typical) the oscillator peak and valley voltage difference is 500 mv typically. to calculate the c t capacitor value for required oscillator frequency, use the equations found in figure 15. an excel based design tool can be found at www.onsemi.com on the ncp3063 product page. figure 14. typical operating waveforms 1 0 output switch 1 0 on off feedback comparator output nominal output voltage level startup operation output voltage timing capacitor, c t i pk comparator output
ncp3063, ncp3063b, ncv3063 http://onsemi.com 8 peak current sense comparator with a voltage ripple gated converter operating under normal conditions, output switch conduction is initiated by the voltage feedback comparator and terminated by the oscillator. abnormal operating conditions occur when the converter output is overloaded or when feedback voltage sensing is lost. under these conditions, the i pk current sense comparator will protect the darlington output switch. the switch current is converted to a voltage by inserting a fractional ohm resistor, r sc , in series with v cc and the darlington output switch. the voltage drop across r sc is monitored by the current sense comparator. if the voltage drop exceeds 200 mv with respect to v cc , the comparator will set the latch and terminate output switch conduction on a cycle ? by ? cycle basis. this comparator/latch configuration ensures that the output switch has only a single on ? time during a given oscillator cycle. real v turn ? off on r s resistor t_delay i1 io di/dt slope i through the darlington switch v ipk(sense) the v ipk(sense) current limit sense voltage threshold is specified at static conditions. in dynamic operation the sensed current turn ? off value depends on comparator response time and di/dt current slope. real v turn ? off on r sc resistor v turn_off v ipk(sense) rs (t_delay di dt) typical i pk comparator response time t_delay is 350 ns. the di/dt current slope is growing with voltage difference on the inductor pins and with decreasing inductor value. it is recommended to check the real max peak current in the application at worst conditions to be sure that the max peak current will never get over the 1.5 a darlington switch current max rating. thermal shutdown internal thermal shutdown circuitry is provided to protect the ic in the event that the maximum junction temperature is exceeded. when activated, typically at 160 c, the output switch is disabled. the temperature sensing circuit is designed with 10 c hysteresis. the switch is enabled again when the chip temperature decreases to at least 150 c threshold. this feature is provided to prevent catastrophic failures from accidental device overheating. it is not intended to be used as a replacement for proper heatsinking. output switch the output switch is designed in a darlington configuration. this allows the application designer to operate at all conditions at high switching speed and low voltage drop. the darlington output switch is designed to switch a maximum of 40 v collector to emitter voltage and current up to 1.5 a. applications figures 16 through 24 show the simplicity and flexibility of the ncp3063. three main converter topologies are demonstrated with actual test data shown below each of the circuit diagrams. figure 15 gives the relevant design equations for the key parameters. additionally, a complete application design aid for the ncp3063 can be found at www.onsemi.com. figures 25 through 31 show typical ncp3063 applications with external transistors. this solution helps to increase output current and helps with efficiency still keeping low cost bill of materials. typical schematics of boost configuration with nmos transistor, buck configuration with pmos transistor and buck configuration with low v ce(sat) pnp are shown. another advantage of using the external transistor is higher operating frequency which can go up to 250 khz. smaller size of the output components such as inductor and capacitor can be used then.
ncp3063, ncp3063b, ncv3063 http://onsemi.com 9 (see notes 9, 10, 11) step ? down step ? up voltage ? inverting t on t off v out v f v in v swce v out v out v f v in v in v swce |v out | v f v in v swce t on t on t off f t on t off 1 t on t off f t on t off 1 t on t off f t on t off 1 c t c t 381.6 10 6 f osc 343 10 12 i l(avg) i out i out t on t off 1 i out t on t off 1 i pk (switch) i l(avg) i l 2 i l(avg) i l 2 i l(avg) i l 2 r sc 0.20 i pk (switch) 0.20 i pk (switch) 0.20 i pk (switch) l v in v swce v out i l t on v in v swce i l t on v in v swce i l t on v ripple(pp) i l 1 8 f c o 2 (esr) 2
t on i out c o i l esr
t on i out c o i l esr v out v th r 2 r 1 1 v th r 2 r 1 1 v th r 2 r 1 1 9. v swce ? darlington switch collector to emitter voltage drop, refer to figures 7, 8, 9 and 10. 10. v f ? output rectifier forward voltage drop. typical value for 1n5819 schottky barrier rectifier is 0.4 v. 11. the calculated t on /t off must not exceed the minimum guaranteed oscillator charge to discharge ratio. the following converter characteristics must be chosen: v in ? nominal operating input voltage. v out ? desired output voltage. i out ? desired output current. i l ? desired peak ? to ? peak inductor ripple current. for maximum output current it is suggested that i l be chosen to be less than 10% of the average inductor current i l(avg) . this will help prevent i pk (switch) from reaching the current limit threshold set by r sc . if the design goal is to use a minimum inductance value, let i l = 2(i l(avg) ). this will proportionally reduce converter output current capability. f ? maximum output switch frequency. v ripple(pp) ? desired peak ? to ? peak output ripple voltage. for best performance the ripple voltage should be kept to a low value since it will directly affect line and load regulation. capacitor c o should be a low equivalent series resistance (esr) electrolytic designed for switching regulator applications. figure 15. design equations
ncp3063, ncp3063b, ncv3063 http://onsemi.com 10 figure 16. typical buck application schematic j204 gnd 1 j203 1 c203 2.2 nf c202 c205 c206 c201 r202 u201 ncp3063 5 3 6 4 8 7 1 2 comp tcap gnd n.c. swc swe r203 r201 0r15 d201 1n5819 j202 gnd 1 j201 1 l201 +v in = +12 v 0.1 f 2k4 1% 3k9 1% 220 f / 50 v + 0.1 f 470 f / 25 v + +v out = +3.3 v / 800 ma v cc i pk 47 h value of components name value l201 47 h, i sat > 1.5 a d201 1 a, 40 v schottky rectifier c202 220 f, 50 v, low esr c205 470 f, 25 v, low esr c203 2.2 nf ceramic capacitor name value r201 150 m , 0.5 w r202 2.40 k r203 3.90 k c201 100 nf ceramic capacitor c202 100 nf ceramic capacitor test results test condition results line regulation v in = 9 v to 12 v, i o = 800 ma 8 mv load regulation v in = 12 v, i o = 80 ma to 800 ma 9 mv output ripple v in = 12 v, i o = 40 ma to 800 ma 85 mv pp efficiency v in = 12 v, i o = 400 ma to 800 ma > 73% short circuit current v in = 12 v, r load = 0.15 1.25 a figure 17. buck demoboard layout figure 18. efficiency vs. output current for the buck demo board at v in = 12 v, v out = 3.3 v, t a = 25 c output load (adc) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 efficiency (%) 76 74 72 70 68 66 64
ncp3063, ncp3063b, ncv3063 http://onsemi.com 11 figure 19. typical boost application schematic j104 gnd 1 j103 1 c103 2.2 nf c102 c105 c106 c101 r102 u101 ncp3063 5 3 6 4 8 7 1 2 comp tcap gnd n.c. swc swe r103 r101 0r15 d101 1n5819 j102 gnd 1 j101 1 l101 +v in = +12 v 0.1 f 1k0 1% 18k0 1% 470 f / 25 v + 0.1 f 330 f / 50 v + +v out = +24 v / 350 ma v cc i pk 100 h value of components name value l101 100 h, i sat > 1.5 a d101 1 a, 40 v schottky rectifier c102 470 f, 25 v, low esr c105 330 f, 50 v, low esr c103 2.2 nf ceramic capacitor name value r101 150 m , 0.5 w r102 1.00 k r103 18.00 k c101 100 nf ceramic capacitor c106 100 nf ceramic capacitor test results test condition results line regulation v in = 9 v to 15 v, i o = 250 ma 2 mv load regulation v in = 12 v, i o = 30 ma to 350 ma 5 mv output ripple v in = 12 v, i o = 10 ma to 350 ma 350 mv pp efficiency v in = 12 v, i o = 50 ma to 350 ma > 85.5% figure 20. boost demoboard layout figure 21. efficiency vs. output current for the boost demo board at v in = 12 v, v out = 24 v, t a = 25 c output load (adc) 0 0.05 0.1 0.15 0.2 0.3 0.4 efficiency (%) 90 85 84 83 82 81 80 0.25 0.35 89 88 87 86
ncp3063, ncp3063b, ncv3063 http://onsemi.com 12 figure 22. typical voltage inverting application schematic j504 gnd 1 j503 1 c503 2.2 nf c502 c501 r502 u501 ncp3063 5 3 6 4 8 7 1 2 comp tcap gnd n.c. swc swe r503 r501 0r15 l501 j502 gnd 1 j501 1 +v in = +5 v 0.1 f 16k9 1% 1k96 1% 330 f / 25 v + 22 h v out = ? 12 v / 100 ma v cc i pk d501 c505 470 f / 35 v + c506 0.1 f 1n5819 value of components name value l501 22 h, i sat > 1.5 a d501 1 a, 40 v schottky rectifier c502 330 f, 25 v, low esr c505 470 f, 35 v, low esr c503 2.2 nf ceramic capacitor name value r501 150 m , 0.5 w r502 16.9 k r503 1.96 k c501 100 nf ceramic capacitor c506 100 nf ceramic capacitor test results test condition results line regulation v in = 4.5 v to 6 v, i o = 50 ma 1.5 mv load regulation v in = 5 v, i o = 10 ma to 100 ma 1.6 mv output ripple v in = 5 v, i o = 0 ma to 100 ma 300 mv pp efficiency v in = 5 v, i o = 100 ma 49.8% short circuit current v in = 5 v, r load = 0.15 0.885 a figure 23. voltage inverting demoboard layout figure 24. efficiency vs. output current for the voltage inverting demo board at v in = +5 v, v out = ? 12 v, t a = 25 c output load (ma dc ) 80 40 20 0 36 38 40 44 46 48 50 52 efficiency (%) 60 100 42
ncp3063, ncp3063b, ncv3063 http://onsemi.com 13 figure 25. typical boost application schematic with external nmos transistor ic1 ncp3063 5 3 6 4 8 7 1 2 r4 v in = 8 ? 18 v/0.6 a v out = 31 v/0.35 a + comp tc gnd n.c. swc swe v cc i pk 1k 1n5819 d1 r3 m18 c2 100n c1 0v gnd c6 100n c7 r8 1k c4 1n2 c5 6n8 r7 470 r5 24k c3 10n r2 1k r1 82m 10 l1 6 2 5 1 4 3 g d s q1 ntd18n06 ic2 bc846bpd 330 330 figure 26. typical efficiency for application shown in figure 25. 70 72 74 76 78 80 82 84 86 6 8 10 12 14 16 18 20 70 72 74 76 78 80 82 84 86 6 8 10 12 14 16 18 20 efficiency (%) input voltage (v) i load = 350 ma external transistor is recommended in applications where wide input voltage ranges and higher power is required. the suitable schematic with an additional nmos transistor and its driving circuit is shown in the figure 25. the driving circuit is controlled from swe pin of the ncp3063 through frequency compensated resistor divider r7/r8. the driver ic2 is on semiconductor low cost dual npn/pnp transistor bc846bpd. its npn transistor is connected as a super diode for charging the gate capacitance. the pnp transistor works as an emitter follower for discharging the gate capacitor. this configuration assures sharp driving edge between 50 ? 100 ns as well as it limits power consumption of r7/r8 divider down to 50 mw. the output current limit is balanced by resistor r3. the fast switching with low r ds(on) nmos transistor will achieve ef ficiencies up to 85% in automotive applications.
ncp3063, ncp3063b, ncv3063 http://onsemi.com 14 figure 27. typical buck application schematic with external pmos transistor ic1 ncp3063 5 3 6 4 8 7 1 2 r3 v in = 8 ? 19 v v out = 3v3/3 a + comp tc gnd n.c. swc swe v cc i pk 1k c2 100n c1 0v gnd c6 100n c7 r8 470 c5 2n2 r6 22k r2 1k7 r1 50m 10 l1 6 1 q2 ntgs4111p c4 6n8 r5 1k d1 1n5822 + 4 3 2 5 t1 bc848cpd 330 330 60 65 70 75 80 85 90 95 100 0 0.5 1 1.5 2 2.5 3 figure 28. ncp3063 efficiency vs. output current for buck external pmos at v out = 3.3 v, f = 220 khz, t a = 25 c efficiency (%) output load (adc) v in = 8 v v in = 18 v figure 27 shows typical buck configuration with external pmos transistor. the principle of driving the q2 gate is the same as shown in figure 27. resistor r6 connected between tc and swe pin provides a pulsed feedback voltage. it is recommended to use this pulsed feedback approach on applications with a wide input voltage range, applications with the input voltage over +12 v or applications with tighter specifications on output ripple. the suitable value of resistor r6 is between 10k ? 68k. the pulse feedback approach increases the operating frequency by about 20%. it also creates more regular switching waveforms with constant operating frequency which results in lower output ripple voltage and improved efficiency. the pulse feedback resistor value has to be selected so that the capacitor charge and discharge currents as listed in the electrical characteristic table, are not exceeded. improper selection will lead to errors in the oscillator operation. the maximum voltage at the tc pin cannot exceed 1.4 v when implementing pulse feedback.
ncp3063, ncp3063b, ncv3063 http://onsemi.com 15 figure 29. typical buck application schematic with external low v ce (sat) pnp transistor ic1 ncp3063 5 3 6 4 8 7 1 2 r2 v in = 8 ? 19 v v out = 3v3/1 a + comp tc gnd n.c. swc swe v cc i pk 1k c2 100n c1 0v gnd c5 100n c6 c3 2n2 r5 33 r3 1k7 r1 150m 33 l1 q1 nss35200 d2 nsr0130 + r4 33 d1 1n5819 100 100 50 55 60 65 70 75 80 85 90 95 100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 figure 30. ncp3063 efficiency vs. output current for external low v ce(sat) at v in = +5 v, f = 160 khz, t a = 25 c efficiency (%) output load (adc) typical application of the buck converter with external bipolar transistor is shown in the figure 29. it is an ideal solution for configurations where the input and output voltage difference is small and high efficiency is required. nss35200, the low v ce ( sat) transistor from on semiconductor will be ideal for applications with 1 a output current, the input voltages up to 15 v and operating frequency 100 ? 150 khz. the switching speed could be improved by using desaturation diode d2.
ncp3063, ncp3063b, ncv3063 http://onsemi.com 16 figure 31. typical schematic of buck converter with rc snubber and pulse feedback ic1 ncp3063 5 3 6 4 8 7 1 2 r3 comp tc gnd n.c. swc swe v cc i pk c1 0v 0v c4 c2 r5 22k r2 r1 l1 d1 c3 r4 4n7 10r in some cases where there are oscillations on the output due to the input/output combination, output load variations or pcb layout a snubber circuit on the swe pin will help minimize the oscillation. typical usage is shown in the figure 31. c3 values can be selected between 2.2 nf and 6.8 nf and r4 can be from 10 to 22 . ordering information device package shipping ? ncp3063pg pdip ? 8 (pb ? free) 50 units / rail ncp3063bpg pdip ? 8 (pb ? free) 50 units / rail ncp3063bmntxg dfn ? 8 (pb ? free) 4000 / tape & reel ncp3063dr2g soic ? 8 (pb ? free) 2500 / tape & reel ncp3063bdr2g soic ? 8 (pb ? free) 2500 / tape & reel ncp3063mntxg dfn ? 8 (pb ? free) 4000 / tape & reel ncv3063pg pdip ? 8 (pb ? free) 50 units / rail NCV3063DR2G soic ? 8 (pb ? free) 2500 / tape & reel ncv3063mntxg dfn ? 8 (pb ? free) 4000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. ncv prefix is for automotive and other applications requiring site and change control.
ncp3063, ncp3063b, ncv3063 http://onsemi.com 17 package dimensions soic ? 8 nb case 751 ? 07 issue aj seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
ncp3063, ncp3063b, ncv3063 http://onsemi.com 18 package dimensions notes: 1. dimension l to center of lead when formed parallel. 2. package contour optional (round or square corners). 3. dimensioning and tolerancing per ansi y14.5m, 1982. style 1: pin 1. ac in 2. dc + in 3. dc - in 4. ac in 5. ground 6. output 7. auxiliary 8. v cc 14 5 8 f note 2 ? a ? ? b ? ? t ? seating plane h j g d k n c l m m a m 0.13 (0.005) b m t dim min max min max inches millimeters a 9.40 10.16 0.370 0.400 b 6.10 6.60 0.240 0.260 c 3.94 4.45 0.155 0.175 d 0.38 0.51 0.015 0.020 f 1.02 1.78 0.040 0.070 g 2.54 bsc 0.100 bsc h 0.76 1.27 0.030 0.050 j 0.20 0.30 0.008 0.012 k 2.92 3.43 0.115 0.135 l 7.62 bsc 0.300 bsc m --- 10 --- 10 n 0.76 1.01 0.030 0.040 8 lead pdip case 626 ? 05 issue l
ncp3063, ncp3063b, ncv3063 http://onsemi.com 19 package dimensions 8 pin dfn, 4x4 case 488af ? 01 issue c dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.25 0.35 d 4.00 bsc d2 1.91 2.21 e 4.00 bsc e2 2.09 2.39 e 0.80 bsc k 0.20 ??? l 0.30 0.50 d b e c 0.15 a c 0.15 2x 2x top view side view bottom view ? ? ?? ? ? ? ? ?? ?? ? c 0.08 c 0.10 ? ? ? ? ?? ? e 8x l k e2 d2 b note 3 1 4 5 8 8x 0.10 c 0.05 c ab pin one reference *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 8x 0.63 2.21 2.39 8x 0.80 pitch 4.30 0.35 l1 detail a l optional constructions ??? ??? ??? ??? 0.15 detail b note 4 detail a dimensions: millimeters package outline on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ncp3063/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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